A data processing device using a memory device such as a Synchronous Dynamic Random Memory (SDRAM) includes a memory access control circuit for controlling data transmission to the memory device. Based on the control by the memory access control circuit, the data processing device transmits data to the memory.
FIG. 6 is a data processing device 400 implemented with a conventional technique.
As shown in FIG. 6, each of bus masters 402 transmits data to a memory device 450 as described below.
Typical commands include a write command and a read command. A master arbitrating unit 410 receives commands from the bus masters 402. The master arbitrating unit 410 selects the commands in a predetermined order when simultaneously receiving multiple commands, and writes, in the order of the selection, the commands in command buffers (a read command buffer 430 and a write command buffer 431) included in a memory control unit 401. When a write command and write data are written in the write command buffer 431 and the data buffer 432, respectively, the command selecting unit 420 issues a write command to an access control unit 440. When the write command is issued from the command selecting unit 420, the access control unit 440 accesses the address of the memory device 450 indicated in the write command. In other words, when the access is made to the memory device 450 with a write command, the write command cannot be issued to the access control unit 440 until the write data of the write command is stored in the data buffer 432.
The data processing device 400 in FIG. 6 separately includes a read command buffer 430 and a write command buffer 431. The command selecting unit 420 selects a command from among write commands and read commands.
Using various techniques, the command selecting unit 420 selects a command from among the write commands in the write command buffer 431 and the read commands in the read command buffer 430.
Patent Literature 1 discloses a technique which compares an address indicated in a write command and another address indicated in a read command, and causes one of the commands to overtake the other.